The present invention relates to semiconductor integrated circuits and, more particularly, to semiconductor integrated circuits which include many wiring portions, such as signal lines, along which flow large AC currents.
In general, memory circuits and microcomputer circuits and the like are supplied activation signals to required portions inside a circuit at a required predetermined cycle time, and are designed so that they operate while activation is being performed. With recent large scale and high speed semiconductor integrated circuits, there is a tendency of reducing this cycle time.
These circuits are normally designed so that the activation signals sent for each cycle time are transmitted via metal wiring, so as to reduce the transmission loss but the width of this metal wiring is becoming finer, with increasing fineness with larger scales and higher speeds.
Furthermore, along with higher speeds there is an increase in the charging and discharging mean current of the signal lines that are configured from metal wiring, coupled with the increasing fineness of the metal wiring, this raises the current density of the current that flows in the metal wiring, and causes problems of reliability of the metal wiring.
Conventional means for lowering the current density so as to counter this deterioration in reliability include widening the width of the metal wiring and having a plural number of metal wires and performing simultaneous drive.
FIG. 1 is a timing chart for describing the transmission timing of general activation signals. This timing chart shows the output for each cycle of activation signals P by an activation circuit that operates by a cycle time (t1). In this figure, the external signal input is, for example, an address input, and the internal signal is, for example, an address transition detection signal. The circuit to which these activation signals P are transmitted is activated in response to these activation signals, and performs charge and discharge.
FIG. 2 is a view showing the structure of wiring 11 that transmits the activation signals P generated by the activation circuit 10. The wiring 11 has a length L and a width W, and has a capacitance CS of the wiring itself and a capacitance CG of the gates and the like of a transistor that configures an operation circuit (not shown in the figure) and that is connected to the wiring. Accordingly, when the activation signals P are transmitted from the activation circuit 10, there may be a problem of the charge and discharge of the capacitances CS and CG.
The mean current ai in one cycle of the wiring 11 that transmits these activation signals P becomes a value (ai=It1/t1) that is the charge and discharge current It1 divided by the cycle time t1 and so there is an increase in the mean current ai as the cycle time t1 becomes shorter, and the current density ai/W (which is a value of ai divided by the wiring width W) of the wiring 11. This decreases reliability.
Shown in FIG. 3 is one measure for increasing the reliability where the width of the wiring itself increased to W' in the new wiring 11' in order to compensate the increase of the mean current ai. However, with this method, the increased wiring width portion also increases the capacitance of the wiring 11' itself so that it becomes CS'. This means that the charge and discharge current increases from It1 to It1' with respect to the increased capacitance, which must also be considered.
As one example, the following considers the case where the capacitance ratio of the capacitances CS and CG is 1:2, and where the cycle time t1 is shortened to 1/2. At this time, the mean current ai doubles and the wiring current density through the wiring also doubles. Accordingly, if the wiring is made larger so that doubled charge and discharge currents flow, then current density conditions that are equivalent to these before the mean current increase will be obtained. On the other hand, the charge and discharge current density for a required voltage becomes a value (I.multidot.t=C.multidot.V) which is proportional to the capacity. Thus, the capacitance (CS'+CG) of the wiring W'.times.L can become twice the original capacitance (CS+CG). Accordingly, in this case, the condition above is satisfied when the capacitance ratio CS':CG becomes 4:2, and it is necessary to have four time the original wiring width W. Because of this, it is necessary to obtain such wide wiring space if the method of FIG. 3 is applied.
In addition, in the condition where the cycle time has become 1/2, measures to reduce the charge and discharge current by compensating the mean current increase by dividing the capacitance of the wiring are proposed. As shown in FIG. 4, this method involves dividing the wiring 11 into n number or portions of wiring 12-1 through 12-n when the length L and the width W of the wiring 11 are maintained constant, and by providing activation signal supply circuits with respect to the respective wiring 12-1 through 12-n as activation circuits 10-1 through 10-n as shown in FIG.4 and then performing simultaneous drive.
In this case, the mean current (It1/n) that flows through a single divided wiring C can be 1/2 and so when the capacitance (CS+CG/n) of the wiring C has become 1/2, the current density conditions are equivalent to those prior to the mean current increase.
These conditions are satisfied when the capacitance ratio CS:CG/n is 1:0.5 and it is necessary to divide the capacitance CG into four parts. Because of this, it is necessary to have an even wider wiring space than for the measure shown in FIG. 3.